Question: Consider the inverter below. When the input VI is high, the switch is closed, and when the input is low, the switch is open. Assume the input is a 5-V TTL pulse with duration T. Assume that capacitor is fully charged for t<0.RD=1kΩ;Ron=250Ω;CL=0.25pF. The circuit is based on the NMOS inverter logic discussed in the class, where capacitor

Consider the inverter below. When the input $V_{\text{I}}is$ high, the switch $is$ closed, and when the input $is$ low, the switch $is$ open. Assume the input $isa5-VTTL$ pulse with duration $T.$ Assume that capacitor $is$ fully charged for $t<0.R_D=1k\Omega$;$R_{on}=250\Omega$;$C_L=0\mathrm{.}25pF.$ The circuit $is$ based $on$ the NMOS inverter logic discussed $in$ the class, where capacitor discharges $to{V}_{OL}$ defined $by$ the MOSFET parameters $R_{on},V_{DD}$ and $R_D$ values.

For $(a)$ and $(b),$ the time range $of$ the plot should cover $0to{5}^{*}T.$

$(a)$ Give $an$ approximate sketch $of$ the output pulse for $T=100ps.[Points10]$

$(b)$ Give $an$ approximate sketch $of$ the output pulse for $T=400ps.[Points10]$

$(c)$ Comment $on$ the level $of$ distortion due $to$ transmission for each pulse duration. $[Points5]$

$(d)$ Determine the propagation delay due $to$ the inverter circuit. $[Points5]$